1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an arrangement of a redundant information storage unit for storing redundant information for specifying a defective memory cell and used for repairing the defective memory cell through replacement with a redundant cell, and a configuration for reading redundant information. More specifically, the present invention relates to arrangement of a redundancy data storage unit in an embedded memory integrated in the same semiconductor substrate with a logic circuit.
2. Description of the Background Art
FIG. 25 schematically shows an entire configuration of a conventional semiconductor memory device. In FIG. 25, the semiconductor memory device includes two memory arrays MAE and MAW. Memory array MAE is divided into memory cell array blocks MBE0 to MBE7 by sense amplifier bands SABE1 to SABE7. Sense amplifier bands SABE0 and SABE8 are arranged outside memory cell array blocks MBE0 and MBE7, respectively.
Memory array MAW is also divided into memory cell array blocks MBW0 to MBW7 by sense amplifier bands SABW1 to SABW7. Sense amplifier bands SABW0 and SABW8 are arranged outside memory cell array blocks MBW0 and MBW7, respectively.
In each of memory cell array blocks MBE0 to MBE7 and MBW0 to MBW7, memory cells are arranged in rows and columns. In each of sense amplifier bands SABE0 to SABE8 and SABW0 to SABW8, sense amplifiers are arranged in correspondence to the columns in corresponding memory cell array blocks. The sense amplifiers are shared by the memory cell array blocks on both sides in a column extending direction (hereinafter, referred to as the column direction).
A decoder band DBD is disposed in the region between memory arrays MAE and MAW. Decoder band DBD is divided into decoder blocks DEB0 to DEB7 in correspondence to the memory cell array blocks. Each of decoder blocks DEB0 to DEB7 includes a row decoder for selecting a row and a column decoder for selecting a column.
In each of memory cell array blocks MBE0 to MBE7 and MBW0 to MBW7, word lines WL are arranged in correspondence to memory cell rows, and bit line pairs (not shown) are arranged in correspondence to the memory cell columns. The word line corresponding to an addressed row in a selected memory cell array block is driven to a selected state by the row decoder. When a corresponding memory cell array block is in a selected state, the column decoder selects a plurality of columns (bit line pairs) concurrently according to a column address signal. Column selection signal lines are extended along a row extending direction (hereinafter, referred to as the row direction).
In each of memory cell array blocks MBE0 to MBE7 and MBW0 to MBW7, a spare row is arranged for repairing a defective row. To repair a defective row, a row fuse circuit which stores a defective row address is provided in each of decoder blocks DEB0 to DEB7.
On the other hand, each of memory arrays MAE and MAW is provided with 64 pairs of I/O lines (data lines) and one spare data line. FIG. 25 shows, as a representative, a pair of I/O lines GIO in memory array MAE.
In correspondence to one pair of I/O lines, 16-bit bit line pairs are provided, for example.
In the operation of selecting a column, 64-bit memory cells are selected in the selected memory cell array block and connected to the corresponding I/O line pairs and a total of 128 bit data is transferred. A pair of spare I/O lines is used to repair a defective row in a unit of I/O line pair. These I/O line pairs GIO are arranged, in each of memory arrays MAE and MAW, extending over the memory cell array blocks in the column direction.
Data path bands DPE and DPW are arranged in correspondence to memory arrays MAE and MAW, respectively. I/O line pairs GIO are coupled to the corresponding data path bands DPE and DPW. Data path bands DPE and DPW each include a redundant replacement circuit for I/O replacement, a write driver/preamplifier for writing/reading internal data, and an input/output buffer circuit.
Each of data path bands DPE and DPW further include a column fuse circuit for storing redundancy data for repairing a defective column through I/O replacement. The column fuse circuits disposed in data path bands DPE and DPW store redundancy data of individual memory array blocks MBE0 to MBE7 and MBW0 to MBW7. Individual redundant replacement for each memory cell array block improves the repairing efficiency in redundant replacement.
In the memory array configuration shown in FIG. 25, in selecting a row, two memory cell array blocks are driven to a selected state in parallel in each of memory arrays MAE and MAW. Specifically, in memory array MAE, two memory cell array blocks are selected at the same positions in lower memory cell array blocks MBE0 to MBE3 and in upper memory cell array blocks MBE4 to MBE7, respectively. Also in memory array MAW, one memory cell array block is selected in lower memory cell array blocks MBW0 to MBW3 and the other memory cell array block is selected a the same position in upper memory cell array blocks MBW4 to MBW7. For example, memory cell array blocks MBW3 and MBW7 are selected at the same time.
A central control band CCTB is disposed in the region between data path bands DPE and DPW. Central control band CCTB includes a main control circuit, an input circuit for address signals and control signals, and a predecode circuit for row addresses. The selection of rows and columns are performed in units of memory cell array blocks under control of the main control circuit disposed in the central control band.
FIGS. 26 and 27 schematically show the structure of redundant replacement for repairing a defective column. In FIGS. 26 and 27, memory cell array blocks MB1 and MB0 are shown representatively. Memory cell array blocks MB0 and MB1 may be included in either one of memory arrays MAE and MAW shown in FIG. 25. Each memory cell array is provided with 64 pairs of I/O lines I/O<0> to I/O<63>. For the 64 pairs of I/O lines I/O<63:0>, a pair of spare I/O lines SI/O is arranged.
Data path band DP includes a shift switch circuit SHT which selectively connects a spare I/O line pair SI/O and I/O line pairs I/O<0:63> with internal data line pairs DB<0:63>. Shift switch circuit SHT disconnects an I/O line pair coupled to a defective memory cell from the internal data bus line pair under control of a shift control signal, not shown, and then connects the spare I/O line pair and the remaining I/O line pairs with the 64-bit internal data path line pairs. Shift switch circuit SHT switches the transfer route of the output signals of a preamplifier and a write driver at the time of accessing the defective cell.
It is assumed that as shown in FIG. 26, there is a defective memory cell MCa to be coupled to I/O line pairs I/O<0> on word line WLa in memory cell array block MB0. In this case, in selecting a column in shift switch circuit SHT, spare I/O line pair SI/O is connected to internal data line pair DB<0> while isolating I/O line pair I/O<0> from the corresponding internal data bus line pair DB<0>. I/O line pairs I/O<1> to I/O<63> are coupled to internal data line pairs DB<1> to DB<63>, respectively. As a result, defective memory cell MCa is replaced by the memory cell coupled to spare I/O line pair SI/O.
Decoder block DEB0 includes a column decoder, and the column selection lines from the column decoder are arranged along the row direction, similarly to word lines WL. Word line WLa is extended in the row direction in each of memory cell array block MB0 and MB1. Therefore, in selecting memory cell array block MB0, a normal memory cell and a spare memory cell are selected at the same time. Column selection by the column decoder enables spare memory cell data to be read to spare I/O line pair SI/O in parallel with the transfer of normal memory cell data in reading data.
It is assumed that memory cell array block MB1 is selected and word line WLb is selected as shown in FIG. 27. In memory cell array block MB1, there is a defective memory cell MCb arranged in correspondence to I/O line pair I/O<1> on the selected word line WLb. In this case, in selecting a column, connection paths are switched in shift switch circuit SHT so as to disconnect I/O line pair I/O<1> from internal data bus line pair DB<1>. Spare I/O line pair SI/O and I/O line pair I/O<0> are connected to internal data line pairs DB<0> and DB<1>, respectively. The remaining I/O line pairs I/O<2:63> are connected to internal data bus line pairs DB<2> to DB<63>, respectively. As a result, defective memory cell MCb is replaced by the spare memory cell.
Therefore, where a column operation (data read or data write; column access) is performed after an ACT operation (row access) to select a row in a memory cell array block, it is determined on which memory cell array block the column operation is performed using the row-related address and the column-related address. Then, a column redundant fuse set is selected from among a total of eight column redundant fuse sets arranged in one-to-one correspondence to the memory cell arrays according to the determination result, so as to perform redundant replacement based on the redundancy data. The row address specifies two memory cell array blocks, and the column address specifies one of the two memory cell array blocks selected at the same time.
In a logic merged memory, the specification of the logic differs depending on a user's application, and different users make different demands on the specification of an embedded memory. Therefore, embedded memory is required to be developed into various kinds of products with the process of the same generation. Specifically, various memory cell array configurations are needed according to requests by the users with respect to the memory capacity, the number of banks, the number of pages, and the number of I/Os (data bit width), for example. Generally, the logic merged memory have the circuitry formed on the assumption that a number of memory cell array blocks are arranged so as to accommodate requests for various kinds of memory cell array configurations. In the present example, the circuit is formed standing on the assumption that 32 memory cell array blocks are arranged at the maximum.
Therefore, it is also necessary that the column fuse sets arranged in data path band DP are provided corresponding to the maximum number of memory cell array blocks. Consequently, in the present example, 32 column fuse sets are arranged.
FIG. 28 schematically shows the arrangement of the column fuse sets. In FIG. 28, data path band DP includes a read circuit arrangement region RKT where a read circuit including a preamplifier is arranged, a write driver arrangement region WKT where a write driver is arranged, and a fuse set arrangement region (band) FB disposed between read circuit arrangement region RKT and write circuit arrangement region WKT.
Fuse set band FB has 32 redundancy data storage circuits FU0 to FU31 arranged, so as to be able to accommodate the maximum number of memory cell arrays. Redundancy data storage circuits FU0 to FU32 each include 7-bit fuse elements and a read circuit that reads fuse programmed data. The 7-bit redundancy data is used because 6 bits are used to select one from 64 I/O line pairs and 1 bit is used to indicate whether redundant replacement is performed or not.
The output signals of redundancy data storage circuits FU0 to FU32 are applied to a shift decoder 910 disposed in a column spare decoder band CSPDB. Shift decoder 910 decodes the applied 7-bit redundancy data and generates spare signals SFTR and SFTW that set the connection path of shift switch circuit SHT shown in FIGS. 26 and 27. Spare signal SFTR sets the output data transfer path of the read circuit including the preamplifier, and spare signal SFTW sets the write data transfer path of the write circuit including the write driver. The separated IO structure is assumed where the internal read data and write data are transferred via separately arranged data lines. When internal write data and internal write data are transferred via the common internal data lines such as I/O lines, a shift control signal of one kind is used.
Spare signals SFTR and SFTW from shift decoder 910 each include signals of 64 bits and set connection paths for 64 I/Os and a spare I/O. As for the shifting operation, two switch circuits for each I/O line pair are arranged and one of the two switch circuits is set conductive in accordance with the shift control signal, thereby establishing the connection path.
Central control band CCTB includes a fuse selection decoder 900 in order to select redundancy data storage circuits FU0 to FU31 disposed in fuse set band FB. Fuse selection decoder 900 is supplied with a row address bit RAB and a column address bit CAB. Row address bit RAB specifies a selected memory cell array block, and the column address bit specifies one of the two memory cell array blocks selected at the same time. Fuse read circuits disposed in redundancy data storage circuits FU0 to FU31 are selected in accordance with a fuse selection trigger signal FTRG from fuse election decoder 900, and the programmed redundancy data is read by the corresponding fuse set and applied to shift decoder 910.
As described above, redundancy data storage circuits FU0 to FU31 each include fuse elements of 7 bits. Fuse elements occupy larger area than transistors and are arranged with some margin in order to prevent scattered fragment generated during blowing from damaging other circuit(s). Therefore, fuse set band FB occupies relatively large area. Since an energy ray such as a laser ray is used for the programming of the elements, it is impossible to arrange interconnection lines above the fuse elements.
Fuse set band FB includes 32 redundancy data storage circuits FU0 to FU31 in correspondence to the largest available number of memory cell arrays. However, in the practical use, when the number of memory cell array blocks to be used is 8, for example, the remaining 24 sets of redundancy data storage circuits are unnecessary. Therefore, when the number of memory cell array blocks is small, useless redundancy data storage circuits are arranged, which causes the problem that the chip area cannot be reduced according to the number of memory cell array blocks, making it impossible to reduce the cost.
There is another problem that interconnection cannot be made efficiently because the fuse elements hinder interconnection layout.
There is still another problem that the number of fuse elements would be restricted if interconnection is made, making it impossible to increase repairing efficiency.